Combining Retiming and Sequential Redundancy Addition and Removal for Sequential Logic Optimization
نویسندگان
چکیده
In this paper a new logic optimization method for sequential synchronous circuits is introduced. For this purpose the current main approaches, “Retiming and Resynthesis” and “Redundancy Addition and Removal” are considered. These techniques have some advantages and limitations that have been theoretically proven by several authors. The goal of the new optimization method is to combine these two techniques to get the best of each one. In particular the paper is focused on area optimization. The algorithm proposed in this paper is efficient and delivers interesting optimization results. Key-Words: Sequential logic optimization, Digital Circuits, Retiming and Resynthesis, Redundancy Addition and Removal
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